Clock switching circuit

ABSTRACT

A clock switching circuit comprises:  
     a select signal generator for receiving a timing signal and clock select signals, used when switching a plurality of types of clocks, and for outputting a plurality of internal select signals; and  
     a clock selector for receiving the plurality of internal select signals and an input clock signal, and for outputting output clock signals corresponding to the internal select signals,  
     wherein, when the internal select signals are switched so as to change the output clock signals from first clock signals to second clock signals, halting of the reception of input clock signals other than input clock signals corresponding to the first and the second clock signals is enabled. With this configuration, the reception of clock signals that are not required for clock switching can be halted.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a clock switching circuit fordynamically switching a plurality of clocks.

[0003] 2. Related Background Art

[0004] A clock switching circuit according to a second embodiment inUnexamined Japanese Patent Publication No. 2001-332961 is conventionallypresent as a circuit wherein no hazard accompanies an output clocksignal when a plurality of clocks are switched. According to thisconventional example, the technique disclosed is intended to prevent theoccurrence of a hazard in the output when a plurality of clock signalsare switched.

[0005] However, two types of clock signals can not be switched in thecircuit disclosed in this publication unless these signals interact witheach other. Thus, when this circuit is employed to cope with theswitching of an increased number of clocks, such as three or four types,all the clocks must be repeatedly and simultaneously supplied to thecircuit, and this constitutes a barrier that forestalls a reduction inthe power consumption.

SUMMARY OF THE INVENTION

[0006] To resolve this problem, according to the present invention, aclock switching circuit comprises:

[0007] a select signal generator for receiving a timing signal and clockselect signals, used when switching a plurality of types of clocks, andfor outputting a plurality of internal select signals; and

[0008] a clock selector for receiving the plurality of internal selectsignals and an input clock signal, and for outputting output clocksignals corresponding to the internal select signals,

[0009] wherein, when the internal select signals are switched so as tochange the output clock signals from first clock signals to second clocksignals, halting of the reception of input clock signals other thaninput clock signals corresponding to the first and the second clocksignals is enabled. With this configuration, the reception of clocksignals that are not required for clock switching can be halted, andpower consumption can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a diagram showing the configuration of a clock switchingcircuit according to a first preferred embodiment of the presentinvention;

[0011]FIG. 2 is a time chart showing the operation of the circuits inFIGS. 1 and 3;

[0012]FIG. 3 is a diagram showing the configuration of a clock switchingcircuit according to a second preferred embodiment of the presentinvention;

[0013]FIG. 4 is a diagram showing the configuration of a clock switchingcircuit according to a third preferred embodiment of the presentinvention;

[0014]FIG. 5 is a diagram showing the shifting of the state of internalselect signals generated by a select signal generator in FIG. 4;

[0015]FIG. 6 is a time chart showing the operation of the circuit inFIG. 4; and

[0016]FIG. 7 is a time chart for when a plurality of signals sel aresimultaneously selected.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] A clock switching circuit according to the present invention willnow be described in detail while referring to the accompanying drawings.

First Preferred Embodiment

[0018]FIG. 1 is a diagram showing the configuration of a clock switchingcircuit according to a first preferred embodiment of the presentinvention. In this configuration, three types of clocks, clk1, clk2 andclk3, are switched. The clock switching circuit comprises: a three-inputOR gate 101; two-input AND gates 102-1, 102-2 and 102-3; reset-inputnegative edge operational D flip-flops (hereinafter referred to asD-FFs) 103-1, 103-2 and 103-3, which have terminals for an input signalD, a clock input CKN, an asynchronous reset signal RN and an outputsignal Q; and low through latches 104-1, 104-2 and 104-3, which haveterminals for an input signal D, a gate control signal GN and a gateoutput signal Q.

[0019] In the reset input negative edge operational D-FFs 103-1, 103-2and 103-3, the gate output signal Q is reset to 0 when the reset inputsignal RN is 0, and in synchronization with the fall of the clock inputCKN, the input signal D is set using the gate output signal Q.

[0020] At the low through latches 104-1, 104-2 and 104-3, when the gatecontrol signal GN is 0, the input signal D is output unchanged by thegate output signal Q, and when the gate control signal GN is 1, thevalue of the gate output signal Q is maintained.

[0021] In FIG. 1, signals sel1, sel2 and sel3 are transmitted to theinput signal terminals D of the low through latches 104-1, 104-2 and104-3, and an output clock signal clkout is transmitted to the gatecontrol signal terminals GN. The gate output signals Q of the lowthrough latches 104-1, 104-2 and 104-3 are transmitted to the terminalsfor the input signals D and the asynchronous reset signals RN of theD-FFs 103-1, 103-2 and 103-3, and clock signals clk1, clk2 and clk3 aretransmitted to the clock signal terminals CKN.

[0022] The gate output signals Q of the D-FFs 103-1, 103-2 and 103-3 arecalled isel1, isel2 and isel3. The signals clk1 and isel1 aretransmitted to the two-input AND gate 102-1; the signals clk2 and isel2are transmitted to the two-input AND gate 102-2; and the signals clk3and isel3 are transmitted to the two-input AND gate 102-3. The outputsignals of the two-input AND gates 102-1, 102-2 and 102-3 aretransmitted as input signals for the three-input OR gate 101, and theoutput of the three-input OR gate 101 serves as a signal clkout. Itshould be noted that only one of the signals sel1, sel2 and sel3 is setto level 1 (1-out-of-3) and two or more signals are not set to level 1at the same time.

[0023]FIG. 2, a time chart for the operation of the circuit in FIG. 1,will now be referred to while an explanation is given for the operationof the circuit. First, while sel1=1 (effective when the clock signalclk1 is selected), sel2=0 and sel3=0 are established, the clock signalsclk1 and clk2 are in the operating state and the clock signal clk3 ishalted. In this state, since isel1=1 and isel2=isel3=0, only the two-ANDgate 102-1 outputs the clock signal clk1, and the three-input OR gate101 outputs this clock signal clk1 as the signal clkout. Thereafter, thesignal clkout is transmitted to the gate control signal terminals GN ofthe low through latches 104-1, 104-2 and 104-3.

[0024] Then, when the above described state is shifted by a controller(not shown) to the state wherein sel1=0, sel2=1 (effective when theclock signal clk2 is selected) and sel3=0, clkout=0 is established forthe state wherein clk1=0. Further, the output of the low through latch104-1 is set to 0, and the asynchronous reset input RN of the D-FF 103-1is set to 0, so that the state is shifted to isel1=0. Since this changeis performed during the period wherein clk1=0, so long as this period isnot shorter than the period wherein the state is changed from clk1=0 toclkout=0 to isel1=0, the signal clkout is not output during the periodfor the next clk1. Furthermore, since the state is not changed toisel1=0 during the period wherein clk1=1, the period for clkout=1, whichis output during the last clk1 period, will not be reduced. Thus, nohazard will accompany the signal clkout.

[0025] The signal isel2 is set to level 1 when the signal clkout is 0,the gate output signal Q of the low through latch 104-2 is 1, the inputsignals D of the D-FFs 103 are 1, and the signal clk2 falls thereafter.Since the signal clkout=0 is established before isel2=1 is set, and ismaintained during the period wherein clk2=0, even after isel2=1 isestablished, the period, at the clock switching time, wherein clkout=0will not be shorter than the period wherein clk2=0, and no hazard isproduced. Then, when the clock signal clk2 rises, the signal isel2=1 isestablished. So long as the period wherein clk2=0 is not extremelyshort, the state wherein isel2=1 is established before the clock signalclk2 rises, so that the period wherein clkout=1 will not be shorter thanthe period wherein clk2=1 and no hazard accompanies the signal clkout.Thus, the operation is not adversely affected even when the clock clk3is halted during the switching from clk1 to clk2.

[0026] In this embodiment, only one of the three types of clock signalsis selected and changed. Therefore, two or more of the signals sel1,sel2 and sel3 are not set to 1 at the same time.

[0027] As is described above, according to the embodiment, the followingeffects are obtained.

[0028] (1) The clocks can be switched without a hazard being produced.

[0029] (2) Since even when clocks other than a target clock are haltedthe clock switching operation is not adversely affected, powerconsumption can be reduced.

[0030] (3) Since a regular structure is employed, the number of clocksto be switched can be easily increased.

[0031] (4) Clock select signals can be switched at an arbitrary timing.

Second Preferred Embodiment

[0032]FIG. 3 is a diagram showing the configuration of a clock switchingcircuit according to a second preferred embodiment of the presentinvention. The clock switching circuit for this embodiment comprises:three-input OR gates 201 and 206; two-input AND gates 202-1, 202-2 and202-3; asynchronous reset D-FFs 203-1, 203-2 and 203-3; and low throughlatches 204-1, 204-2, 204-3, 205-1, 205-2 and 205-3. The D-FFs and thelow through latches are the same as those used for the first embodiment.

[0033] For the D-FFs 203-1, 203-2 and 203-3, gate output signals Q arereset to 0 when reset input signals RN are 0, and in synchronizationwith the fall of input clock signals CKN, the values of input signals Dare set for output. For the low through latches 204-1, 204-2, 204-3,205-1, 205-2 and 205-3, input signals D are output unchanged when gatecontrol signals GN are 0, while the values of gate output signals Q aremaintained when the gate control signals GN are 1.

[0034] Signals sel1, sel2 and sel3 are transmitted to the terminals forthe input signals D of the low through latches 205-1, 205-2 and 205-3,and input clock signals clk1, clk2 and clk3 are transmitted to the gatecontrol signal terminals GN. The gate output signals Q of the lowthrough latches 205-1, 205-2 and 205-3 are transmitted to the inputsignal terminals D of the low through latches 204-1, 204-2 and 204-3,and the output of the three-input OR gate 206 is transmitted to the gatecontrol signal terminals GN.

[0035] The gate output signals Q of the low through latches 204-1, 204-2and 204-3 are transmitted to the input signal terminals D of the D-FFs203-1, 203-2 and 203-3. The gate output signals Q of the low throughlatches 205-1, 205-2 and 205-3 are transmitted to the asynchronous resetsignal terminals RN, and the clock signals clk1, clk2 and clk3 aretransmitted to the clock signal terminals CN. The gate output signals Qare called isel1, isel2 and isel 3.

[0036] The signals clk1 and isel1 are transmitted to the input terminalsof the two-input AND gate 202-1, the signals clk2 and isel2 aretransmitted to the input terminals of the two-input AND gate 202-2, andthe signals clk3 and isel3 are transmitted to the input terminals of thetwo-input AND gate 202-3. The output signals of the two-AND gates 202-1,202-2 and 202-3 are transmitted to the input terminals of the inputterminals of the three-input OR gate 201, and the output signal of thethree-input OR gate 201 serves as an output clock signal clkout. Thesignals isel1, isel2 and isel3 are transmitted to the input terminals ofthe three-input OR gate 206, and the output signal of the three-input ORgate 206 is transmitted to the gate control signal terminals GN of thelow through latches 204-1, 204-2 and 204-3.

[0037] Each signal sel1, sel2 or sel3 is a clock select signal, which isa 1-out-of-3 signal such that only one of the signals can have a valueof 1 at one time.

[0038] The operation of the clock switching circuit in FIG. 3 will nowbe described. Since the operating time chart for this circuit is thesame as that in FIG. 2, the time chart in FIG. 2, is employed forexplaining the operation.

[0039] First, while sel1=1, sel2 0 and sel3=0 are established, the clocksignals clk1, clk2 and clk3 are received at respective timings. Since inthis state isel1=1, isel2=0 and isel3=0, the two-input AND gates 202-1,202-2 and 202-3 and the three-input OR gate 201 constitute amultiplexer, which selects the clock signal clk1 and outputs it to theterminal clkout.

[0040] When the state is shifted to sel1=0, sel2=1 and sel3=0, whileduring the period wherein clk1=0, the gate output signal Q of the lowthrough latch 205-1 is changed to 0, as is the reset input signal RN ofthe D-FF 203-1, so that the state is shifted to isel1=0. This change isperformed during the period wherein clk1=0, so long as this period isnot shorter than the delay for the low through latch 205-1 and the delayduring which the D-FF 203-01 is reset. Therefore, the next clock signalclk1 will not be output to the terminal clkout. Further, since the stateis not changed to isel1=0 during the period wherein clk1=1, the periodwherein clkout=1, which is output during the last period wherein clk1=1,is not reduced. Thus, no hazard accompanies the signal clkout.

[0041] The signal isel2=1 is established when clk2=0 is temporarilyestablished, the gate output signal Q of the low through latch 205-2 ischanged to level 1, all the signals isel1, isel2 and isel3 are set to 0,the output of the three-input OR gate 206 is set to 0, the gate outputsignal Q of the low through latch 204-2 is set to 0, and thereafter, thesignal clk2 falls. Since the signal clkout of 0 has already been outputbefore isel2=1 is established, and since clkout=0 is maintained duringthe period wherein clk2=0, even after the state is changed to isel2=1,the period, at the clock switching time, wherein clkout=0 will not beshorter than the period wherein clk2=0, and no hazard is produced. Sinceisel2=1 is established when clk2 falls, the period wherein clkout=1 isnot shorter than the period wherein clk2=1, and no hazard accompaniesthe signal clkout. The clock signal clk3 may be halted while the clocksignal clk1 is switched to the clock signal clk2, because the signalclk3 does not adversely affect the operation.

[0042] When the correct input condition (1-out-of-3) for the signalssel1, sel2 and sel3 is not satisfied, and a plurality of these signalssel are simultaneously set to 1, as is shown in FIG. 3, sel1=1, sel2=0and sel3=0 and isel1=1, isel2=0 and isel3=0 are established. Even whensel2 and sel3 are changed to 1 while the clock signal clk1 is selected,the output of the three-input OR gate 206 is 1, so that the gate outputsignals Q of the low through latches 204-2 and 204-3 are maintained as0. Therefore, the signals isel2 and isel3 do not change to 1, and theclock signal clk2 or clk3 is not included in the signal clkout. This iscompensated for so long as a plurality of the clock select signals sel1,sel2 and sel3 are not 0 when all the clocks have not been selected,i.e., isel1=0, isel2=0 and isel3=0 is established.

[0043] As is described above, according to the second embodiment, inaddition to the effects obtained in the first embodiment, even when theclock select signal does not correspond to the 1-out-of-3 condition, theoutput of an abnormal clock does not occur so long as two or more selectsignals are not effective at the same time when all the clocks are notselected.

Third Preferred Embodiment

[0044]FIG. 4 is a diagram showing the configuration of a clock switchingcircuit according to a third preferred embodiment of the presentinvention. This diagram is a circuit diagram that is more generalizedthan are those in FIGS. 1 and 3. According to this circuit, input clocksare clk1, clk2 and clk3, internal select signals are isel1, isel2 andisel3, and an output clock is clkout. A select signal generator 303receives a timing signal and a clock select signal, and generatesinternal select signals.

[0045] The clock switching circuit for this embodiment comprises: athree-input OR gate 303, and two-input AND gates 302-1, 302-2 and 302-3.The two-input AND gates 302-1, 302-2 and 302-3 respectively receive theclock signals clk1, clk2 and clk3 and the internal select signals isel1,isel2 and isel3, and transmit the output signals to the three-input ORgate 301. The output of the three-input OR gate 301 serves as the outputclock clkout.

[0046] The internal select signal (isel1, isel2, isel3) can be either a1-out-of-3 signal of (1, 0, 0), (0, 1, 0) or (0, 0, 1), or the initialstate (0, 0, 0), wherein all the signals are 0, and this state change isshown in FIG. 5.

[0047] As is shown in FIG. 5, only when the clock signals clk1, clk2 andclk3 are falling can the state (initial state) of (isel1, isel2,isel3)=(0, 0, 0) be changed to each of the states (1, 0, 0), (0, 1, 0)and (0, 0, 1). Further, only when clk1=0 is established can the state(isel1, isel2, isel3)=(1, 0, 0) be changed to isel1=0. Similarly, onlywhen clk2=0 can the state (0, 1, 0) be changed to isel2=2, and only whenclk3=0 can the state (0, 0, 1) be changed to isel3=0.

[0048] The select signal generator 303 employs the timing signal and theclock select signal to generate the internal select signals isel1, isel2and isel3 that satisfy the above condition. The timing signalscorrespond to the signals clk1, clk2, clk3 and clkout in the firstembodiment, or the signals clk1, clk2 and clk3 and the output of thethree-input OR gate 206 that receives the signals isel1, isel2 and isel3in the second embodiment. It should be noted, however, that these aremerely examples, and another combination of signals may be employed.Furthermore, while the clock select signals sel1, sel2 and sel3 are usedin the first and second embodiments, these are not always 1-out-of-3signals.

[0049]FIG. 6 is a time chart for the operation of the clock switchingcircuit in FIG. 4. The operation of the clock switching circuit in FIG.4 will now be described while referring to FIG. 6.

[0050] First, in the state wherein (isel1, isel2, isel3)=(1, 0, 0), theclock signals clk1, clk2 and clk3 are received at the individualtimings. In this state, the two-input AND gates 302-1, 302-2 and 302-3and the three-input OR gate 301 constitute a multiplexer, which selectsthe signal clk1 and outputs it to the terminal clkout.

[0051] The clock signal is changed from the signal clk1 to clk2, and theselect signal generator 303 shifts isel1 to 0 during the period whereinclk1 is 0. Since this shifting is performed during the period whereinclk1=0, the next clk1=1 is not output to the terminal clkout so long asbetween the select signals there are no great delay differences.Further, the period wherein clkout=1, which is output in the last periodof clk1, is not reduced. Therefore, no hazard accompanies the outputclock clkout. In this manner, the state (0, 0, 0) is obtained in theinternal state shifting diagram.

[0052] The select signal generator 303 sets isel2 to 1 when the fallingof the signal clk2 occurs once or more after all the clocks have notbeen selected. As a result, the period wherein clkout=0 at the clockswitching time will not be shorter than the period wherein clk2=0, andno hazard is produced. Then, when the signal clk2 falls, isel2=1 isestablished, and since isel2=1 is set before the signal clk2 rises, solong as the period wherein clk2=0 is not extremely short, the periodwherein clkout=1 will not be shorter than the period wherein clk2=1, andno hazard will accompany the clock clkout. The signal clk3 may be haltedduring the period wherein the signal clk1 is switched to clk2 becausethe signal clk3 does not adversely affect the operation.

[0053] As is described above, according to the effects obtained by thethird embodiment, (1) the clocks can be switched without a hazardoccurring, and (2) a clock other than the clocks to be switched can behalted.

[0054] The present invention is not limited to these preferredembodiments, and can be variously modified based on the subject of theinvention. For example, in the third embodiment, other gates, such asNAND gates, may be used to replace the three-input OR gate and thetwo-input AND gates.

[0055] Further, the clocks have been switched in the state whereinclkout=0. But when the three-input OR gate 301 is replaced with an ANDgate, the two-input AND gates 302 are replaced with OR gates, and theinternal select signals isel1, isel2 and isel3 are changed to 2-out-of-3signals of (0, 1, 1), (1, 0, 1) or (1, 1, 0), or signals of (1, 1, 1),the clocks can be switched in the state wherein clkout=1.

[0056] In addition, although only three types of clocks have beenemployed for the first to third embodiment, an arbitrary number ofclocks may be employed.

What is claimed is:
 1. A clock switching circuit comprising: a selectsignal generator for receiving a timing signal and clock select signals,used when switching a plurality of types of clocks, and for outputting aplurality of internal select signals; and a clock selector for receivingthe plurality of internal select signals and an input clock signal, andfor outputting output clock signals corresponding to the internal selectsignals, wherein, when the internal select signals are switched so as tochange the output clock signals from first clock signals to second clocksignals, halting of the reception of input clock signals other thaninput clock signals corresponding to the first and the second clocksignals is enabled.
 2. A clock switching circuit according to claim 1,wherein a state that is represented by a set of the internal selectsignals generated by the select signal generator is begun with theinitial state, wherein all the internal select signals are locally “0”,and is then changed to a first state wherein, as the logical level ofone of the input clock signals is changed, only a corresponding internalselect signal is locally “1”; and wherein, when the input clock signalis locally “0”, the first state is changed to a second state representedby a different set of the internal select signals.
 3. A clock switchingcircuit according to claim 1, wherein the timing signal includes aplurality of types of input clock signals and a single output clocksignal; and wherein the select signal generator includes, in a numberequivalent to the count of clock signals to be switched, clockgeneration blocks that each have a first circuit, for latching the clockselect signal by using the output clock signal, and a second circuit,for receiving an output signal for the first circuit at an asynchronousreset input terminal and a data set input terminal, and for outputtingthe internal select signal in synchronization with the input clocksignal.
 4. A clock switching circuit according to claim 3, wherein thefirst circuit is a low through latch for passing the clock select signalunchanged when a gate control terminal GN for receiving an output clockis logically “0”, and for maintaining data when the gate controlterminal GN is logically “1”; and wherein the second circuit is anegative edge operational D flip-flop that is triggered upon the fall ofthe input clock signal.
 5. A clock switching circuit according to claim1, wherein the timing signal includes a plurality of types of inputclock signals, and a logical sum output signal for the internal selectsignals; and wherein the select signal generator is formed of, in anumber equivalent to the count of the clock signals to be switched,clock generation blocks that each include a first circuit, for latchingthe clock select signal by using an input clock signal, a secondcircuit, for latching the output of the first circuit by using thelogical sum output signal, and a third circuit, for receiving the outputof the first circuit at an asynchronous reset input terminal and theoutput of the second circuit at a data set input terminal and foroutputting the internal select signal in synchronization with the inputclock signal.
 6. A clock switch circuit according to claim 5, whereinthe first and the second circuits are low through latches according toclaim 4, and the third circuit is a D flip-flop according to claim 4.